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LTC4150 Coulomb Counter/ Battery Gas Gauge
FEATURES

DESCRIPTIO
Indicates Charge Quantity and Polarity 50mV Sense Voltage Range Precision Timer Capacitor or Crystal Not Required 2.7V to 8.5V Operation High Side Sense 32.55Hz/V Charge Count Frequency 1.5A Shutdown Current 10-Pin MSOP Package
APPLICATIO S

The LTC(R)4150 measures battery depletion and charging in handheld PC and portable product applications. The device monitors current through an external sense resistor between the battery's positive terminal and the battery's load or charger. A voltage-to-frequency converter transforms the current sense voltage into a series of output pulses at the interrupt pin. These pulses correspond to a fixed quantity of charge flowing into or out of the battery. The part also indicates charge polarity as the battery is depleted or charged. The LTC4150 is intended for 1-cell or 2-cell Li-Ion and 3-cell to 6-cell NiCd or NiMH applications.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Battery Chargers Palmtop Computers and PDAs Cellular Telephones and Wireless Modems
TYPICAL APPLICATIO
Integral Nonlinearity, % of Full Scale
RSENSE CHARGER LOAD 4.7F RL SENSE - SENSE + VDD CF+ 4.7F CF- LTC4150 INT CLR POL GND SHDN
4150 TA01a
0.5 0.4 0.3
RL
+
ERROR (% FULL SCALE)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25 0 25 CURRENT SENSE VOLTAGE (mV) 50
CHG
DISCHG
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4150 TA01b
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LTC4150
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW SENSE + SENSE - CF+ CF- 1 2 3 4 SHDN 5 10 9 8 7 6 INT CLR VDD GND POL
Supply Voltage (VDD) ...................................- 0.3V to 9V Input Voltage Range Digital Inputs (CLR, SHDN) ....... - 0.3V to (VDD + 0.3) SENSE -, SENSE + , CF -, CF + ........ - 0.3V to (VDD + 0.3) Output Voltage Range Digital Outputs (INT, POL) .......................- 0.3V to 9V Operating Temperature Range LTC4150CMS .......................................... 0C to 70C LTC4150IMS ..................................... -40C TO 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4150CMS LTC4150IMS MS PART MARKING LTQW
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 160C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 2.7V and 8.5V unless otherwise noted.
SYMBOL VIL VIH VOL ILEAK VOS PARAMETER Digital Input Low Voltage, CLR, SHDN Digital Input High Voltage, CLR, SHDN Digital Output Low Voltage, INT, POL Digital Output Leakage Current, INT, POL Differential Offset Voltage (Note 4) IOL = 1.6mA, VDD = 2.7V VINT = VPOL = 8.5V VDD = 4.0V
ELECTRICAL CHARACTERISTICS
CONDITIONS

MIN 1.9
TYP
MAX 0.7 0.5
UNITS V V V A V V V V V V V V k V A A A A Hz/V Hz/V %/V %/ C % % s s
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0.01
1 100 150 100 150 150 200
VDD = 8.0V
VDD = 2.7V to 8.5V
VSENSE(CM) VSENSE RIDR VUVLO IDD IDD(SD)
Sense Voltage Common Mode Input Range Sense Voltage Differential Input Range Average Differential Input Resistance, Across SENSE + and SENSE - Undervoltage Lockout Threshold Supply Current, Operating Supply Current, Shutdown SENSE + - SENSE - VDD = 4.1V (Note 3) VDD Rising VDD = 8.5V VDD = 2.7V VDD = 8.5V VDD = 2.7V VSENSE = 50mV to - 50mV, 2.7V VDD 8.5V 2.7V VDD 8.5V (Note 2)

VDD - 0.06 - 0.05 155 270 2.5 115 80
VDD + 0.06 0.05 390 2.7 140 100 10 1.5

Power Supply Current
AC Characteristics GVF GVF(VDD) INL tCLR tINT Voltage to Frequency Gain Gain Variation with Supply Integral Nonlinearity

32.0 31.8 0 - 0.03 - 0.4 - 0.5 20
32.55
33.1 33.3 0.5 0.03 0.4 0.5
GVF(TEMP) Gain Variation with Temperature
CLR Pulse Width to Reset INT, INT and CLR Not Connected INT Low Time, INT Connected to CLR
Figure 2 Figure 3, CL = 15pF
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LTC4150
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design and not tested in production. Note 3: Measured at least 20ms after power on. Note 4: Tested in feedback loop to SENSE + and SENSE -.
otherwise noted.)
TYPICAL PERFOR A CE CHARACTERISTICS
Voltage to Frequency Gain vs Supply Voltage
+1.00 +0.75 +1.00 +0.75
GVF ERROR (% OF TYPICAL)
+0.50 +0.25 VSENSE = 25mV 0 -0.25 -0.50 -0.75 -1.00 2 3 4 5 6 VDD (V) 7 8 9
4150 G01
GVF ERROR (% OF TYPICAL)
IDD (A) 125
VSENSE = 50mV
Shutdown IDD vs VDD
6 5 4
VOL (mV)
3 2 1 0 2 3 4 5 6 VDD (V)
4150 G04
200 150 100 50 0
INT PIN
UVLO (V)
IDD (A)
7
UW
8 9
(Specifications are at TA = 25C, unless
Voltage to Frequency Gain vs Temperature
VSENSE = 50mV 140
Operating IDD vs VDD
+0.50 +0.25 0 -0.25 -0.50 -0.75 -1.00 -50 VDD = 2.7V VDD = 8.5V
120
100
80
60 -25 0 25 50 75 TEMPERATURE (C) 100 2 3 4 5 6 7 VDD (V) 8 9 10
4150 G02
4150 G03
Digital Output Low Voltage vs VDD
400 350 300 250 POL PIN IOL = 1.6mA 2.60 2.59 2.58 2.57 2.56 2.55 2.54 2.53 2 3 4 5 6 VDD (V) 7 8 9
4150 G05
Undervoltage Lockout Threshold vs Temperature
RISING EDGE
10
2.52 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
4150 G06
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LTC4150
PI FU CTIO S
SENSE+ (Pin 1): Positive Sense Input. This is the noninverting current sense input. Connect SENSE+ to the load and charger side of the sense resistor. Full-scale current sense input is 50mV. SENSE+ must be within 60mV of VDD for proper operation. SENSE- (Pin 2): Negative Sense Input. This is the inverting current sense input. Connect SENSE- to the positive battery terminal side of the sense resistor. Full-scale current sense input is 50mV. SENSE- must be within 60mV of VDD for proper operation. CF+ (Pin 3): Filter Capacitor Positive Input. A capacitor connected between CF+ and CF- filters and averages noise and fast battery current variations. A 4.7F value is recommended. If filtering is not desired, leave CF+ and CF- unconnected. CF- (Pin 4): Filter Capacitor Negative Input. A capacitor connected between CF+ and CF- filters and averages noise and fast battery current variations. A 4.7F value is recommended. If filtering is not desired, leave CF+ and CF- unconnected. SHDN (Pin 5): Shutdown Digital Input. When asserted low, SHDN forces the LTC4150 into its low current consumption power-down mode and resets the part. In applications with logic supply VCC > VDD, a resistive divider must be used between SHDN and the logic which drives it. See the Applications Information section. POL (Pin 6): Battery Current Polarity Open-Drain Output. POL indicates the most recent battery current polarity when INT is high. A low state indicates the current is flowing out of the battery while high impedance means the current is going into the battery. POL latches its state when INT is asserted low. POL is an open-drain output and can be pulled up to any logic supply up to 9V. In shutdown, POL is high impedance. GND (Pin 7): Ground. Connect directly to the negative battery terminal. VDD (Pin 8): Positive Power Supply. Connect to the load and charger side of the sense resistor. SENSE+ also connects to VDD. VDD operating range is 2.7V to 8.5V. Bypass VDD with 4.7F capacitor. CLR (Pin 9): Clear Interrupt Digital Input. When asserted low for more than 20s, CLR resets INT high. Charge counting is unaffected. INT may be directly connected to CLR. In this case the LTC4150 will capture each assertion of INT and wait at least 1s before resetting it. This ensures that INT pulses low for at least 1s but gives automatic INT reset. In applications with a logic supply VCC > VDD, a resistive divider must be used between INT and CLR. See the Applications Information section. INT (Pin 10): Charge Count Interrupt Open-Drain Output. INT latches low every 1/(VSENSE * GVF) seconds and is reset by a low pulse at CLR. INT is an open-drain output and can be pulled up to any logic supply of up to 9V. In shutdown INT is high impedance.
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LTC4150
BLOCK DIAGRA
CHARGER
LOAD VDD S3 100pF 2k S1 200k CF+ 200k AMPLIFIER
SENSE +
RSENSE
CF CF- 2k SENSE - 200k
IBAT
GND
4150 F01
TI I G DIAGRA S
CLR 50% 50%
tCLR
INT 50% 50%
INT
tINT
4150 F02
4150 F03
Figure 2. CLR Pulse Width to Reset INT, CLR and INT Not Connected
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REFHI 1.7V INT
+ -
CONTROL LOGIC
OFLOW/ UFLOW COUNTER
S R
Q
- +
CLR UP/DN CHARGE POL DISCHARGE
+ -
POLARITY DETECTION
S2
REFLO 0.95V
SHDN
Figure 1. Block Diagram
UW
Figure 3. INT Minimum Pulse Width, CLR and INT Connected
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LTC4150
OPERATIO
Charge is the time integral of current. The LTC4150 measures battery current by monitoring the voltage developed across a sense resistor and then integrates this information in several stages to infer charge. The Block Diagram shows the stages described below. As each unit of charge passes into or out of the battery, the LTC4150 INT pin interrupts an external microcontroller and the POL pin reports the polarity of the charge unit. The external microcontroller then resets INT with the CLR input in preparation for the next interrupt issued by the LTC4150. The value of each charge unit is determined by the sense resistor value and the sense voltage to interupt frequency gain GVF of the LTC4150. Power-On and Start-Up Initialization When power is first applied to the LTC4150, all internal circuitry is reset. After an initialization interval, the LTC4150 begins counting charge. This interval depends on VDD and the voltage across the sense resistor but will be at least 5ms. It may take an additional 80ms for the LTC4150 to accurately track the sense voltage. An internal undervoltage lockout circuit monitors VDD and resets all circuitry when VDD falls below 2.5V. Asserting SHDN low also resets the LTC4150's internal circuitry and reduces the supply current to 1.5A. In this condition, POL and INT outputs are high impedance. The LTC4150 resumes counting after another initialization interval. Shutdown minimizes battery drain when both the charger and load are off.
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CHARGE COUNTING First, the current measurement is filtered by capacitor CF connected across pins CF+ and CF-. This averages fast changes in current arising from ripple, noise and spikes in the load or charging current. Second, the filter's output is applied to an integrator with the amplifier and 100pF capacitor at its core. When the integrator output ramps to REFHI or REFLO levels, switches S1 and S2 reverse the ramp direction. By observing the condition of S1 and S2 and the ramp direction, polarity is determined. The integrating interval is trimmed to 600s at 50mV full-scale sense voltage. Third, a counter is incremented or decremented every time the integrator changes ramp direction. The counter effectively increases integration time by a factor of 1024, greatly reducing microcontroller overhead required to service interrupts from the LTC4150. At each counter under or overflow, the INT output latches low, flagging a microcontroller. Simultaneously, the POL output is latched to indicate the polarity of the observed charge. With this information, the microcontroller can total the charge over long periods of time, developing an accurate estimate of the battery's condition. Once the interrupt is recognized, the microcontroller resets INT with a low going pulse on CLR and awaits the next interrupt. Alternatively, INT can drive CLR.
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LTC4150
APPLICATIO S I FOR ATIO
SENSE VOLTAGE INPUT AND FILTERS Since the overall integration time is set by internally trimming the LTC4150, no external timing capacitor or trimming is necessary. The only external component that affects the transfer function of interrupts per coulomb of charge is the sense resistor, RSENSE. The common mode range for the SENSE+ and SENSE- pins is VDD 60mV, with a maximum differential voltage range of 50mV. SENSE+ is normally tied to VDD, so there is no common mode issue when SENSE- operates within the 50mV differential limit relative to SENSE+. Choose RSENSE to provide 50mV drop at maximum charge or discharge current, whichever is greater. Calculate RSENSE from:
RSENSE = 50mV IMAX
The sense input range is small (50mV) to minimize the loss across RSENSE. To preserve accuracy, use Kelvin connections at RSENSE. The external filter capacitor CF operates against a total onchip resistance of 4k to form a lowpass filter that averages battery current and improves accuracy in the presence of noise, spikes and ripple. 4.7F is recommended for general applications but can be extended to higher values as long as the capacitor's leakage is low. A 10nA leakage is roughly equivalent to the input offset error of the integrator. Ceramic capacitors are suitable for this use. Switching regulators are a particular concern because they generate high levels of current ripple which may flow through the battery. The VDD and SENSE+ connection to the charger and load should be bypassed by at least 4.7F at the LTC4150 if a switching regulator is present. The LTC4150 maintains high accuracy even when Burst Mode(R) switching regulators are used. Burst pulse "on" levels must be within the specified differential input voltage range of 50mV as measured at CF+ and CF-. To retain accurate charge information, the LTC4150 must remain enabled during Burst Mode operation. If the LTC4150 shuts down or VDD drops below 2.5V, the part resets and charge information is lost.
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Coulomb Counting The LTC4150's transfer function is quantified as a voltage to frequency gain GVF, where output frequency is the number of interrupts per second and input voltage is the differential drive VSENSE across SENSE+ and SENSE-. The number of interrupts per second will be: f = GVF * VSENSE where VSENSE = IBATTERY * RSENSE Therefore, f = GVF * IBATTERY * RSENSE (4) Since I * t = Q, coulombs of battery charge per INT pulse can be derived from Equation 4: (3) (2) (1)
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One INT =
1 Coulombs GVF * RSENSE
(5)
Battery capacity is most often expressed in ampere-hours. 1Ah = 3600 Coulombs Combining Equations 5 and 6: (6)
One INT =
or
1 3600 * GVF * RSENSE
[Ah]
(7)
1Ah = 3600 * GVF * RSENSE Interrupts
(8)
The charge measurement may be further scaled within the microcontroller. However, the number of interrupts, coulombs or Ah all represent battery charge. The LTC4150's transfer function is set only by the value of the sense resistor and the gain GVF. Once RSENSE is selected using Equation 1, the charge per interrupt can be determined from Equation 5 or 7. Note that RSENSE is not chosen to set the relationship between ampere-hours of battery charge and number of interrupts issued by the LTC4150. Rather, RSENSE is chosen to keep the maximum sense voltage equal to or less than the LTC4150's 50mV full-scale sense input.
Burst Mode is registered trademark of Linear Technology Corporation.
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LTC4150
APPLICATIO S I FOR ATIO
INT, POL and CLR
INT asserts low each time the LTC4150 measures a unit of charge. At the same time, POL is latched to indicate the polarity of the charge unit. The integrator and counter continue running, so the microcontroller must service and clear the interrupt before another unit of charge accumulates. Otherwise, one measurement will be lost. The time available between interrupts is the reciprocal of Equation 2:
Time per INT Assertion = 1 GVF *VSENSE
At 50mV full scale, the minimum time available is 596ms. To be conservative and accommodate for small, unexpected excursions above the 50mV sense voltage limit, the microcontroller should process the interrupt and polarity information and clear INT within 500ms. Toggling CLR low for at least 20s resets INT high and unlatches POL. Since the LTC4150's integrator and counter operate independently of the INT and POL latches, no charge information is lost during the latched period or while CLR is low. Charge/discharge information continues to accumulate during those intervals and accuracy is unaffected. Once cleared, INT idles in a high state and POL indicates real-time polarity of the battery current. POL high indicates charge flowing into the battery and low indicates charge flowing out. Indication of a polarity change requires at least:
tPOL =
2 GVF * 1024 *VSENSE
where VSENSE is the smallest sense voltage magnitude before and after the polarity change. Open-drain outputs POL and INT can sink IOL = 1.6mA at VOL = 0.5V. The minimum pull-up resistance for these pins should be: RL > (VCC - 0.5) / 1.6mA (11) where VCC is the logic supply voltage. Because speed isn't an issue, pull-up resistors of 10k or higher are adequate.
LTC4150
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Interfacing to INT, POL, CLR and SHDN The LTC4150 operates directly from the battery, while in most cases the microcontroller supply comes from some separate, regulated source. This poses no problem for INT and POL because they are open-drain outputs and can be pulled up to any voltage 9V or less, regardless of the voltage applied to the LTC4150's VDD. CLR and SHDN inputs require special attention. To drive them, the microcontroller or external logic must generate a minimum logic high level of 1.9V. The maximum input level for these pins is VDD + 0.3V. If the microcontroller's supply is more than this, resistive dividers must be used on CLR and SHDN. The schematic in Figure 6 shows an application with INT driving CLR and microcontroller VCC > VDD. The resistive dividers on CLR and SHDN keep the voltages at these pins within the LTC4150's VDD range. Choose R2 and R1 so that: (R1 + R2) 50RL 1.9 V R1 VCC VDD (Minimum) R1 + R2 (12) (13) (9) Equation 13 also applies to the selection of R3 and R4. The minimum VDD is the lowest supply to the LTC4150 when the battery powering it is at its lowest discharged voltage. When the battery is removed in any application, the CLR and SHDN inputs are unpredictable. INT and POL outputs may be erratic and should be ignored until after the battery is replaced. If desired, the simple logic of Figure 4 may be used to derive separate charge and discharge pulse trains from INT and POL.
INT CLR CHARGE
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DISCHARGE POL
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Figure 4. Unravelling Polarity-- Separate Charge and Discharge Outputs
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LTC4150
APPLICATIO S I FOR ATIO
AUTOMATIC CHARGE COUNT INTERRUPT AND CLEAR In applications where a CLR pulse is unavailable, it's easy to make the LTC4150 run autonomously, as shown in Figures 5 and 6. If the microcontroller VCC is less than or equal to the battery VDD, INT may be directly connected to CLR, as in Figure 5. The only requirement is that the microcontroller should be able to provide a high logic level of 1.9V to SHDN. If the microcontroller VCC is greater than
1 RSENSE 2 2.7V TO 8.5V + BATTERY CF 4.7F 3
SENSE +
LTC4150 CLR SENSE - CF+ CF- SHDN POL VDD GND
4 5
Figure 5. Application with INT Direct Drive of CLR and Separate Microprocessor Supply VCC VDD
1 RSENSE 2 BATTERY VBATTERY < VCC
SENSE +
LTC4150 CLR 3 CF 4.7F SENSE - CF+ CF- SHDN POL VDD GND
+
4 5
Figure 6. Application with INT Driving CLR and Separate Microprocessor Supply VCC > VDD
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the battery VDD, use Figure 6. The resistor dividers on CLR and SHDN keep the voltages at these pins within the LTC4150's VDD range. Choose an RL value using Equation 11 and R1-R4 values using Equation 13. In either application, the LTC4150 will capture the first assertion of INT and wait at least 1s before resetting it. This insures that INT pulses low for at least 1s but gives automatic INT reset.
POWER-DOWN SWITCH LOAD PROCESSOR VCC CL 47F RL INT 10 9 8 7 C2 4.7F P RL 6
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POWER-DOWN SWITCH LOAD PROCESSOR VCC CL 47F
RL INT 10 9 8 7 C2 4.7F R2
RL
R1
P
6 SHUTDOWN R4
R3
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LTC4150
APPLICATIO S I FOR ATIO
PC BOARD LAYOUT SUGGESTIONS
Keep all traces as short as possible to minimize noise and inaccuracy. The supply bypass capacitor C2 should be placed close to the LTC4150. The 4.7F filter capacitor CF should be placed close the CF+ and CF- pins and should be a low leakage, unpolarized type. Use a 4-wire Kelvin sense connection for the sense resistor, locating it close to the LTC4150 with short sense traces to the SENSE+ and SENSE- pins and longer force lines to the battery pack and powered load, see Figure 7.
TYPICAL APPLICATIO S
Figure 8 shows a typical application designed for a single cell lithium-ion battery and 500mA maximum load current. Use Equation 1 to calculate RSENSE = 0.05V / 0.5A = 0.1. With RSENSE = 0.1, Equation 7 shows that each interrupt corresponds to 0.085mAh. Equation 14, derived from Equation 2, gives the number of INT assertions for average battery current, IBATT, over a time, t, in seconds: INT Assertions = GVF * IBATT * RSENSE * t (14) Loading the battery so that 51.5mA is drawn from it over 600 seconds results in 100 INT assertions. For an 800mAh battery, this is (51.5mA * 1/6h) / 800mAh = 11% of the battery's capacity. With a microcontroller supply = 5V, Equation 11 gives RL > 2.875k. The nearest standard value is 3k. From Equation 12, RL = 3k gives R1 + R2 equal to 150.5k. A single cell lithium-ion battery can discharge as low as 2.7V. From Equation 13, select R1 = 75k; the nearest standard value for R2 is 76.8k. Also from Equation 13, we choose R3 = 75k and R4 = 76.8k.
1 RSENSE 0.1 SINGLE-CELL Li-Ion 3.0V ~ 4.2V
SENSE +
LTC4150 CLR 2 3 CF 4.7F SENSE - CF+ CF- SHDN POL VDD GND
+
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Figure 8. Typical Application, Single Cell Lithium-Ion Battery
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TO CHARGER PIN 1 RSENSE LTC4150
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TO BATTERY
Figure 7. Kelvin Connection on SENSE Resistor
POWER-DOWN SWITCH LOAD 5.0V CL 47F
INT
10 9 8 7 C2 4.7F
RL 3k R2 76.8k R1 75k
RL 3k
P
6 SHUTDOWN R4 76.8k R3 75k
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LTC4150
PACKAGE DESCRIPTIO U
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005) 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF DETAIL "A" 0 - 6 TYP 12345 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.127 0.076 (.005 .003)
MSOP (MS) 0603
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
1.10 (.043) MAX
0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.50 (.0197) BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC4150
TYPICAL APPLICATIO S
CHARGER LOAD SENSE + 1.2 1.1 100m
SENSE RESISTANCE = 0.0852 IMAX = 588mA 10,000 PULSES = 1Ah
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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INT
CD40110B
LTC4150 CLR SENSE - CD40110B
+
CD40110B
CD40110B
CD40110B
4150 F09
Figure 9. Ampere-Hour Gauge
4150fa LT/TP 1004 1K REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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